The present invention is directed toward semiconductor circuits, and more particularly to complementary bipolar inverter circuits and methods for fabrication such circuits.
Digital logic has been dominated by silicon CMOS circuits. It's desirable to reduce the operating voltage for CMOS circuits due to increased power consumption and heating in scaled CMOS technologies. However, CMOS performance is reaching a limit due to its poor signal-to-noise margins at low operating voltages (i.e., less than 0.5 volts).
In a bipolar inverter circuit, the output current is exponentially dependent on the input voltage, giving much higher transconductance and potentially faster switching speed than CMOS. However, conventional vertical bipolar transistors are generally not suitable for high density digital logic because of their large footprint due to isolation structure, their large parasitic capacitance due to the relatively large base-collector junction area, and associated minority carrier charge storage when biased in the saturation mode, that is when the collector-base diode is forward biased.